Lesson 10: VHDL vs Verilog vs Schematic
There are many ways to create a CPLD or FPGA image. The most common methods are with VHDL, Verilog or schematic capture. In this lesson we’ll explore and compare all three.
Discussion is open, so please let us hear the answers to your homework either here on P2PU or in our forums. Or, if you have other questions, shout them out loud!